1. Field of the Invention
The present invention relates generally to semiconductor device design, and more particularly, to a fuse configuration for a semiconductor storage device having a modified capacitor border layout and method of formation thereof.
2. Description of the Related Art
It is well-known to use fuses for permanent storage of data in semiconductor storage devices, i.e., memory devices, and for programming redundancy in semiconductor storage devices of this type. In the former case, the state of the fuse (xe2x80x9cconductingxe2x80x9d or xe2x80x9cnon-conductingxe2x80x9d) establishes a data value (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d), while in the latter case, if there is a defective storage cell, a redundant storage cell is connected into the circuit by activating the fuse.
Fuses generally consist of a conducting layer, for example, doped polycrystalline silicon, TiN, Al, or a similar suitable material that can be blown or melted through the action of energy, by means of which a previously existing conducting connection is broken. It is, however, also conceivable to use a dielectric material as a fuse separating two interconnect layers. A conduction path is generated by breaking down a dielectric layer in a non-conducting state in order to create a conducting connection, i.e., a fused connection. The activation of energy may be brought about, for example, by irradiating a fuse with electromagnetic irradiation, or else simply by passing a relatively heavy current through a particular fuse, in order to cause it to melt.
Referring to FIGS. 1A and 1B, a conventional fuse configuration 10 for a semiconductor device is shown. The fuse configuration 10 includes a lower electrode 12, formed in a dielectric layer 14, a fuse element 16, and an upper electrode 18 connected to contact, or metal line, 20. Although not drawn to scale, the conventional layout of the fuse configuration 10 is constructed where the perimeter of the upper electrode 18 is larger than the perimeter of the lower electrode 12. FIG. 1B illustrates this concept with a bottom plan view of the fuse configuration with the dielectric layer 14 removed for clarity.
During the formation of the fuse configuration 10, lower electrode 12 is formed in dielectric layer 14 and a standard polish process, such as a chemical mechanical polishing (CMP), is performed to planarize surface 22 and remove any conductive material from the surface 22. However, as a result of the polishing process, the lower electrode 12 protrudes slightly from the dielectric layer 14, thus forming a little step 24 with a sharp metallic edge. This edge 24 exists along the entire perimeter of the lower electrode 12 and the fuse element 16 has its smallest thickness along this edge 24. When the fuse is employed as a non-conducting connection and voltage is applied to the fuse, leakage of current can occur at edge 24 or a relatively large electric field will be produced across the fuse element 16 at edge 24 and thus cause early breakdown and/or reliability issues of the fuse. For example, the fuse element 16 may breakdown causing a short to occur between the lower electrode 12 and upper electrode 18 rendering the connection unusable.
Accordingly, it is an aspect of the present invention to provide a fuse configuration for a semiconductor storage device and method of formation thereof which overcome the disadvantages of the prior art fuse configurations.
It is another aspect of the present invention to provide a fuse configuration which eliminates a concentrated high electric field region across a fuse element.
According to the present invention, a new and improved fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first electrode having a first cross-sectional area defined by a first perimeter; a fuse element for coupling the first electrode to a second electrode; and the second electrode having a second cross-sectional area defined by a second perimeter, the first perimeter of the first electrode being larger than the second perimeter.
According to another aspect of the present invention, a method for forming a fuse configuration for a semiconductor device is also provided. The method includes the steps of providing a first electrode having a first cross-sectional area defined by a first perimeter; and coupling the first electrode to a second electrode having a second cross-sectional area defined by a second perimeter, by a fuse element; the first perimeter being larger than the second perimeter. The providing a first electrode step further includes depositing a dielectric layer on a substrate of the semiconductor device; etching a cavity in the dielectric layer, the cavity being of the first cross-sectional area; depositing a first conductive material in the cavity to form the first electrode having the cross-sectional area of the cavity. The coupling step further includes the steps of depositing an isolating layer on the conductive material. Additionally, the coupling step further includes the steps of depositing a second conductive layer on the isolating layer; and processing the second conductive layer to form the second electrode having the second cross-sectional area.